----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:20:22 03/28/2009 
-- Design Name: 
-- Module Name:    PWMtop - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


---------------------------------------------------------------------
--Right motor connection to J1
--Left Motor connection to J7
--See UCF File for PMOD A1 pin mapping
----------------------------------------------------------------------




entity PWMtop is
    Port ( --uncomment next two lines when inserting into module and feed pwm values in
			  --can turn these into 2 8 bits values or one 16 bit value if we want
			  LeftPWMin : in  STD_LOGIC_VECTOR (6 downto 0);
           RightPWMin : in  STD_LOGIC_VECTOR (6 downto 0);
			  --uncomment next two lines when inserting into module and feed control signals for each wheel
			  Leftin : in STD_LOGIC; --If 1 go forward else backward
			  Rightin : in STD_LOGIC; --IF 1 go forward else backward
			  -----------------------------------------------------------
           LeftPWMout : out  STD_LOGIC; --PWM for left wheel
           RightPWMout : out  STD_LOGIC; --PWM for Right wheel
			  Leftout : out STD_LOGIC_VECTOR (1 downto 0);
			  Rightout : out STD_LOGIC_VECTOR (1 downto 0);
			  
			  --comment next two lines and corresponding entries in ucf file when using in module
			  -- these are just for testing
			  ------------------------------------------
			  --swt : in STD_LOGIC_VECTOR (7 downto 0);
			  --btn : in STD_LOGIC_VECTOR (3 downto 0);
			  ------------------------------------------
			  
			  mclk : in  STD_LOGIC);
end PWMtop;


architecture Behavioral of PWMtop is


--comment next two lines when inserting into module
--these are only for testing
------------------------------------------------------
--signal LeftPWMin : STD_LOGIC_VECTOR (6 downto 0);
--signal RightPWMin : STD_LOGIC_VECTOR (6 downto 0);
-------------------------------------------------------

signal counter : STD_LOGIC_VECTOR (6 downto 0);
signal clk : std_logic;

begin

clk <= mclk;

Motors: process (clk)
begin

	if rising_edge(clk) then
		counter <= counter + 1;

----------------------------------------------
--comment all out if inserting in module only for testing	
--		if swt(7) = '1' then
--			LeftPWMin <= swt(6 downto 0);
--		else
--			RightPWMin <= swt(6 downto 0);
--		end if;
--		

		
------------------------------------------------

--uncomment when inserting module
--		if LeftPWMin = '1' then
			
	end if;
	
end process Motors;

--change this when inserting in module
-----------------------------------------									
--Rightout <= "01" when btn(0) = '1' else
--				  "10";
		
Rightout <= "01" when Rightin = '1' else
				  "10";
		
												
--Leftout <= "01" when btn(3) = '1' else
--				  "10";

Leftout <= "01" when Leftin = '1' else
			  "10";

-----------------------------------------




Leftmotor: LeftPWMout <= '1' when LeftPWMin(6 downto 0) > counter(6 downto 0)
else '0';

Rightmotor: RightPWMout <= '1' when RightPWMin(6 downto 0) > counter(6 downto 0)
else '0';



--led(7 downto 0) <= LeftPWMout & "000000" & RightPWMout;
--Leftout <= Leftcontrol;
--Rightout <= Rightcontrol;

end Behavioral;

